DESIGN FOR TESTABILITY WITH HW-SW CODESIGN

Abstract

Current trends in the development of design automation tools aim at a radical increase in productivity by offering highly automated design tools. As applications include even critical control applications, dependability becomes an important design issue. A novel approach supporting concurrent diagnostic engineering using a dataflow behavioural description is presented in this paper. The basic idea of this new method is the extension of the descriptions of the functional elements with the models of fault effects and fault propagation at each level of the hardware-software codesign hierarchy, thus allowing design for testability of digital computing systems. Using the presented approach test generation can be done cuncurrently with the system design and not only in the back-end design phase as it had been done previously. For test generation purposes the generalized forms of the well-known logic gate level test design algorithms call be used.