A COMPABILITY BASED ALLOCATION METHOD IN HIGH LEVEL SYNTHESIS

Abstract

This paper presents a model and a method for the allocation during the high level datapath synthesis of pipelined ASIC architectures starting with a behavioral description of the system consisting of theoretical operational units with arbitrary operation duration. As a part of the Scheduling and Allocation Method (SAM), a compatibility relation is used for determining the operations to be allocated in one processor element. The aim of the procedure is to reduce the number of processors that are necessary for the realization of the theoretical operational units. The method presented in this paper can provide a better solution to the resource allocation problem in many cases by handling the conditional branches. The constraints for the types of processors to be applied can be different depending upon the hardware resources.