USING LOGIC SYNTHESIS TOOLS FOR TEXAS INSTRUMENTS FP GAs

Abstract

High density PLDs (Programmable Logic Devices) and FP GAs (Field-Programmable Gate Arrays) are becoming more and more popular in the field of logic design. Their ultimate advantages - no NRE (Non-REcurring) costs, fast time-to-market, in-house design, etc. - are being combined with ever increasing speeds and densities. Up to now the tradi- tional FPGA design technique has been schematics. But hardware complexity has outrun schematics with chips so complex that the graphical representation of the circuit shows only a web of connectivity, not the functionality of the design. For this reason more and more engineers are turning to Hardware Description Languages (HDL) for digital design. The prospect of using Logic Synthesis Tools is one of the main reasons which make HDLs attractive for designers. These tools take a behavioural, or other type of HDL description, and produce a technology specific net list for an FPGA or for another type of ASIC. The effectiveness of the Logic Synthesis Tools is a key factor in deciding against or in favour of HDLs and synthesis. The synthesis powers of two programs were tested and compared using three sample designs. The meaning of FPGAs, HDLs and Logic Synthesis are ex- plained in more detail in the first chapters of the article. The results of logic synthesis are in the second part. The source codes, command line arguments and batch (or script) files used are also given.