SWITCHED-CAPACITOR CIRCUITS WITH REDUCED INFLUENCES OF PARASITIC CAPACITANCES, SWITCH RESISTANCES AND AMPLIFIER NON-IDEALITIES

Abstract

Two design techniques are described for decreasing and possibly eliminating the effects of element imperfections in switched-capacitor (SC) circuits. The first technique is devoted to the operational amplifier non-idealities. It is centered on decreasing the number of amplifiers in the circuits by multiplexing their use. The second approach is based on the minimization of the sum of the square of the differences between the time (or the frequency) response of the circuit with and without non-idealities. This technique can be used to control over the effects of finite switch resistances, finite gain-bandwidth product of the amplifiers as well as parasitic capacitances. Computer results have revealed that the responses of the optimized circuits are nearly the same as that of the ideal ones. Illustrative examples are given illustrating the efficiency of the proposed techniques.