EFFICIENCY TEST OF AUTOMATIC TEST PATTERN GENERATION METHODS

Abstract

Automatic Test Pattern Generation (ATPG) is unavoidable for large combinational circuits, However, since ATPG is a known NP-complet problem, this is a very CPU-time consuming process, Therefore choosing the optimal ATPG algorithm for an industrial test generation system can be an important question, However, this question cannot be easily answered because of the implementational and evaluation differences of the published algorithms, This paper presents a software frame, where any ATPG method and their heuristic can be easily implemented allowing a correct comparison between different methods, On the other hand the known ATPG methods cannot be ordered by quality, because their efficiency depends on the properties of the examined circuit. Therefore it seems to be reasonable to develop a hibrid strategy whose effectivity is independent of the circuit properties and near to the known strategies, The presented frame is an ideal environment for developing such a new method, Experimental results are also presented on some implemented algorithms and heuristics using a variety of MSI components and ISCAS'85 benchmark circuits,