Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture

  • Jagadeesh Kokila ORCID
    Affiliation

    Department of Computer Science and Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu, 620015, India

  • Arjun Murali Das
    Affiliation

    Department of Computer Science and Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu, 620015, India

  • Basha Shameedha Begum
    Affiliation

    Department of Computer Science and Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu, 620015, India

  • Natarajan Ramasubramanian
    Affiliation

    Department of Computer Science and Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu, 620015, India

Abstract

Security is becoming an important issue in the recent System on Chip (SoC) design due to various hardware attacks that can affect manufacturers, system designers or end users. Major issues include hardware Trojan attack, hardware intellectual property (IP) theft, such as an illegal sale or use of firm intellectual property cores or integrated circuits (ICs) and physical attacks. A hybrid model consisting of Arbiter PUF and Butterfly PUF are used to generate random responses which are fed to a Finite State Machine (FSM). A three-level FSM was designed to generate the signature correctly to authenticate IPs. The results were obtained with the help of three Intellectual Property (IP) cores – Zedboard OLED IP, ISCAS’89 s1423 Benchmark IP and a Full Adder IP. A 16-bit arbiter PUF and Butterfly PUF have been implemented on a 28nm FPGA. The average execution time to generate hardware signature for three IP cores was found to be 4.78 seconds (5 iterations) which is considerably low.

Keywords: Physical Unclonable Function (PUF), Intellectual Property (IP), System on Chip (SoC), Finite State Machine (FSM), Zedboard
Published online
2019-06-14
How to Cite
Kokila, J., Murali Das, A., Begum, B. S., Ramasubramanian, N. “Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture”, Periodica Polytechnica Electrical Engineering and Computer Science, 63(4), pp. 244-253, 2019. https://doi.org/10.3311/PPee.13424
Section
Articles