Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation

Authors

  • Rekib Uddin Ahmed
    Affiliation

    Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong-793003, India

  • Prabir Saha
    Affiliation

    Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong-793003, India

https://doi.org/10.3311/PPee.14279

Abstract

In the present era, down scaling of complementary metal-oxide-semiconductor (CMOS) technology has lead the metal-oxide-semiconductor field-effect-transistor's (MOSFET) sizes to nanometer regime which in turn experiencing difficulties due to the effect of physical and technological perspective. Double-gate (DG) MOSFET is considered as a promising device to reduce the shortcoming and shrink down towards nanometer domain. This paper proposes electrostatic potential distribution and drain current models for the lightly doped symmetrical p-channel DG MOSFET. The analytic solution of potential distribution is derived by solving the 2D Poisson's equation incorporated with hole density through the superposition method. The drain current model has been explored by incorporating physical effects like threshold-voltage roll-off, channel length modulation and surface roughness scattering. Functionality of the models has been calculated in MATLAB and the obtained results are verified and compared with state of the art literature.

Keywords:

channel length modulation, cross-over point, drain-current, potential distribution, p-channel, subthreshold slope, threshold voltage

Published Online

2019-12-17

How to Cite

Ahmed, R. U., Saha, P. “Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation”, Periodica Polytechnica Electrical Engineering and Computer Science, 64(1), pp. 106–114, 2020. https://doi.org/10.3311/PPee.14279

Issue

Section

Articles