High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes

  • Ved Mitra Department of Computer Science and Engineering, Malaviya National Institute of Technology, Jawahar Lal Nehru Marg, Jaipur, Rajasthan – 302017, India
  • Mahesh C. Govil National Institute of Technology Sikkim, Ravangla, South Sikkim, Sikkim – 737139, India
  • Girdhari Singh Department of Computer Science and Engineering, Malaviya National Institute of Technology, Jawahar Lal Nehru Marg, Jaipur, Rajasthan – 302017, India
  • Sanjeev Agrawal Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jawahar Lal Nehru Marg, Jaipur, Rajasthan – 302017, India

Abstract

Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performance of SPA. Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. Fixed-point, 9-bit quantization scheme is used to achieve better error performance. Another significant contribution of this work is the pipelining of the proposed decoder architectures to further enhance the overall throughput. These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ASIC. Synthesis and simulation results have shown the better performance, throughput and effectiveness of the proposed designs.

Keywords: low-density parity-check (LDPC) codes, sum-product decoding algorithm (SPA), projective geometry (PG), Galois fields (GF), FPGA, ASIC
Published online
2019-12-07
How to Cite
Mitra, V., Govil, M., Singh, G. and Agrawal, S. (ONLINE) “High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes”, Periodica Polytechnica Electrical Engineering and Computer Science. https://doi.org/10.3311/PPee.14807.
Section
Articles